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CY7C1031 CY7C1032
64K x 18 Synchronous Cache RAM
Features
* Supports 66-MHz Pentium(R) microprocessor cache systems with zero wait states * 64K by 18 common I/O * Fast clock-to-output times -- 8.5 ns * Two-bit wraparound counter supporting Pentium microprocessor and 486 burst sequence (7C1031) * Two-bit wraparound counter supporting linear burst sequence (7C1032) * Separate processor and controller address strobes * Synchronous self-timed write * Direct interface with the processor and external cache controller * Asynchronous output enable * I/Os capable of 3.3V operation * JEDEC-standard pinout * 52-pin PLCC packaging
Functional Description
The CY7C1031 and CY7C1032 are 64K by 18 synchronous cache RAMs designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.5 ns. A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. The CY7C1031 is designed for Intel(R) Pentium and i486 CPUbased systems; its counter follows the burst sequence of the Pentium and the i486 processors. The CY7C1032 is architected for processors with linear burst sequences. Burst accesses can be initiated with the processor address strobe (ADSP) or the cache controller address strobe (ADSC) inputs. Address advancement is controlled by the address advancement (ADV) input. A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip select input and an asynchronous output enable input provide easy control for bank selection and output three-state control.
Logic Block Diagram
18 DATA IN REGISTER ADDR REG 9 14 16 2 ADV ADV LOGIC 2 64K X 9 64K X 9 RAM ARRAY RAM ARRAY 9 DQ8 DQ9 VCCQ VSSQ DQ10 DQ11 DQ12 DQ13 VSSQ VCCQ DQ14 DQ15 DP1[1] 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Configuration
PLCC Top View
WH WL ADSC ADSP ADV CLK OE A8 A9 A10 A6 A7 CS
16 A15 -A0
14
CLK ADSP ADSC CS WH WL TIMING CONTROL
WH WL 9 9
7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C1031 7C1032 40 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 A5 A 4 A 3 A 2 A1 A0 GND V CC A 15 A14 A13 A12 A11
[1]
DP0 DQ7 DQ6 VCCQ VSSQ DQ5 DQ4 DQ3 DQ2 VSSQ VCCQ DQ1 DQ0
18 DQ15 - DQ0 DP1 - DP0 OE 1031-2 1031-1
Selection Guide
7C1031-8 7C1032-8 Maximum Access Time (ns) Maximum Operating Current (mA) Commercial
Intel and Pentium are trademarks of Intel Corporation. Note: 1. DP0 and DP1 are functionally equivalent to DQx.
7C1031-10 7C1032-10 10 280
7C1031-12 7C1032-12 12 230
8.5 280
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 November 30, 1999
CY7C1031 CY7C1032
Functional Description (continued)
Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CS is LOW and (2) ADSP is LOW. ADSP-triggered write cycles are completed in two clock periods. The address at A0 through A15 is loaded into the address register and address advancement logic and delivered to the RAM core. The write signal is ignored in this cycle because the cache tag or other external logic uses this clock period to perform address comparisons or protection checks. If the write is allowed to proceed, the write input to the CY7C1031 and CY7C1032 will be pulled LOW before the next clock rise. ADSP is ignored if CS is HIGH. If WH, WL, or both are LOW at the next clock rise, information presented at DQ 0-DQ15 and DP0-DP 1 will be written into the location specified by the address advancement logic. WL controls the writing of DQ0-DQ7 and DP0 while WH controls the writing of DQ8-DQ15 and DP1. Because the CY7C1031 and CY7C1032 are common-I/O devices, the output enable signal (OE) must be deasserted before data from the CPU is delivered to DQ 0-DQ15 and DP0-DP1. As a safety precaution, the appropriate data lines are three-stated in the cycle where WH, WL, or both are sampled LOW, regardless of the state of the OE input. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at rising edge of the clock: (1) CS is LOW, (2) ADSC is LOW, and (3) WH or WL are LOW. ADSC-triggered accesses are completed in a single clock cycle. The address at A 0 through A15 is loaded into the address register and address advancement logic and delivered to the RAM core. Information presented at DQ 0-DQ15 and DP0-DP1 will be written into the location specified by the address advancement logic. Since the CY7C1031 and the CY7C1032 are common-I/O devices, the output enable signal (OE) must be deasserted before data from the cache controller is delivered to the data and parity lines. As a safety precaution, the appropriate data and parity lines are three-stated in the cycle where WH and WL are sampled LOW regardless of the state of the OE input. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CS is LOW, (2) ADSP or ADSC is LOW, and (3) WH and WL are HIGH. The address at A0 through A15 is stored into the address advancement logic and delivered to the RAM core. If the output enable (OE) signal is asserted (LOW), data will be available at the data outputs a maximum of 8.5 ns after clock rise. ADSP is ignored if CS is HIGH.
Burst Sequences
The CY7C1031 provides a 2-bit wraparound counter, fed by pins A0-A1, that implements the Intel 80486 and Pentium processor's address burst sequence (see Table 1). Note that the burst sequence depends on the first burst address. Table 1. Counter Implementation for the Intel Pentium/80486 Processor's Sequence First Address AX + 1, Ax 00 01 10 11 Second Address AX + 1, Ax 01 00 11 10 Third Address AX + 1, Ax 10 11 00 01 Fourth Address AX + 1, Ax 11 10 01 00
The CY7C1032 provides a two-bit wraparound counter, fed by pins A 0-A1, that implements a linear address burst sequence (see Table 2). Table 2. Counter Implementation for a Linear Sequence First Address AX + 1, Ax 00 01 10 11 Second Address AX + 1, Ax 01 10 11 00 Third Address AX + 1, Ax 10 11 00 01 Fourth Address AX + 1, Ax 11 00 01 10
Application Example
Figure 1 shows a 512-Kbyte secondary cache for the Pentium microprocessor using four CY7C1031 cache RAMs.
2
CY7C1031 CY7C1032
512 KB 66-MHz OSC
CLK ADR DATA ADS PENTIUM PROCESSOR
CLK ADR DATA ADSP ADSC ADV OE WH, WL WH, WL 2 2 2 WH2 , WL2 2 WH3 , WL3 INTERFACE TO MAIN MEMORY WH, WL WH, WL 7C1031
CLK ADR CD CACHE TAG DATA MATCH DIRTY VALID
WH1 , CLK ADSC ADV OE WH0 , WL1 WL0 ADR DATA ADSP CACHE CONTROLLER MATCH DIRTY VALID
Figure 1. Cache Using Four CY7C1031s
Pin Definitions
Signal Name VCC VCCQ GND VSSQ CLK A15 - A0 ADSP ADSC WH WL ADV OE CS DQ15-DQ0 DP1-DP0 Input Input Input Input Input Input Input Input Input Input Input Input Input Input/Output Input/Output Type # of Pins 1 4 1 4 1 16 1 1 1 1 1 1 1 16 2 +5V Power +5V or 3.3V (Outputs) Ground Ground (Outputs) Clock Address Address Strobe from Processor Address Strobe from Cache Controller Write Enable - High Byte Write Enable - Low Byte Advance Output Enable Chip Select Regular Data Parity Data Description
3
CY7C1031 CY7C1032
Pin Descriptions
Signal Name Input Signals CLK I Clock signal. It is used to capture the address, the data to be written, and the following control signals: ADSP, ADSC, CS, WH, WL, and ADV. It is also used to advance the on-chip auto-addressincrement logic (when the appropriate control signals have been set). Sixteen address lines used to select one of 64K locations. They are captured in an on-chip register on the rising edge of CLK if ADSP or ADSC is LOW. The rising edge of the clock also loads the lower two address lines, A1-A0, into the on-chip auto-address-increment logic if ADSP or ADSC is LOW. Address strobe from processor. This signal is sampled at the rising edge of CLK. When this input and/or ADSC is asserted, A0-A15 will be captured in the on-chip address register. It also allows the lower two address bits to be loaded into the on-chip auto-address-increment logic. If both ADSP and ADSC are asserted at the rising edge of CLK, only ADSP will be recognized. The ADSP input should be connected to the ADS output of the processor. ADSP is ignored when CS is HIGH. Address strobe from cache controller. This signal is sampled at the rising edge of CLK. When this input and/or ADSP is asserted, A0-A15 will be captured in the on-chip address register. It also allows the lower two address bits to be loaded into the on-chip auto-address-increment logic. The ADSC input should not be connected to the ADS output of the processor. Write signal for the high-order half of the RAM array. This signal is sampled by the rising edge of CLK. If WH is sampled as LOW, i.e., asserted, the control logic will perform a self-timed write of DQ15-DQ8 and DP 1 from the on-chip data register into the selected RAM location. There is one exception to this. If ADSP, WH, and CS are asserted (LOW) at the rising edge of CLK, the write signal, WH, is ignored. Note that ADSP has no effect on WH if CS is HIGH. Write signal for the low-order half of the RAM array. This signal is sampled by the rising edge of CLK. If WL is sampled as LOW, i.e., asserted, the control logic will perform a self-timed write of DQ7-DQ0 and DP0 from the on-chip data register into the selected RAM location. There is one exception to this. If ADSP, WL, and CS are asserted (LOW) at the rising edge of CLK, the write signal, WL, is ignored. Note that ADSP has no effect on WL if CS is HIGH. Advance. This signal is sampled by the rising edge of CLK. When it is asserted, it automatically increments the 2-bit on-chip auto-address-increment counter. In the CY7C1032, the address will be incremented linearly. In the CY7C1031, the address will be incremented according to the Pentium/486 burst sequence. This signal is ignored if ADSP or ADSC is asserted concurrently with CS. Note that ADSP has no effect on ADV if CS is HIGH. Chip select. This signal is sampled by the rising edge of CLK. If CS is HIGH and ADSC is LOW, the SRAM is deselected. If CS is LOW and ADSC or ADSP is LOW, a new address is captured by the address register. If CS is HIGH, ADSP is ignored. Output enable. This signal is an asynchronous input that controls the direction of the data I/O pins. If OE is asserted (LOW), the data pins are outputs, and the SRAM can be read (as long as CS was asserted when it was sampled at the beginning of the cycle). If OE is deasserted (HIGH), the data I/O pins will be three-stated, functioning as inputs, and the SRAM can be written. I/O Description
A15-A0
I
ADSP
I
ADSC
I
WH
I
WL
I
ADV
I
CS
I
OE
I
Bidirectional Signals
DQ15-DQ0
I/O
Sixteen bidirectional data I/O lines. DQ 15-DQ8 are inputs to and outputs from the high-order half of the RAM array, while DQ 7-DQ0 are inputs to and outputs from the low-order half of the RAM array. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they carry the data read from the selected location in the RAM array. The direction of the data pins is controlled by OE: when OE is HIGH, the data pins are three-stated and can be used as inputs; when OE is LOW, the data pins are driven by the output buffers and are outputs. DQ15-DQ8 and DQ7-DQ0 are also three-stated when WH and WL, respectively, is sampled LOW at clock rise. Two bidirectional data I/O lines. These operate in exactly the same manner as DQ15-DQ0, but are named differently because their primary purpose is to store parity bits, while the DQs' primary purpose is to store ordinary data bits. DP1 is an input to and an output from the high-order half of the RAM array, while DP0 is an input to and an output from the lower-order half of the RAM array.
DP1-DP0
I/O
4
CY7C1031 CY7C1032
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................-65C to +150C Ambient Temperature with Power Applied ...............................................-55C to +125C Supply Voltage on VCC Relative to GND................ -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ...............................................-0.5V to VCC + 0.5V DC Input Voltage ...........................................-0.5V to VCC + 0.5V
[2]
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA
Operating Range
Range Com'l Ambient Temperature[3] 0C to +70C VCC 5V 5% VCCQ 3.0V to VCC
Electrical Characteristics Over the Operating Range[4]
7C1031-8 7C1032-8 Parameter VOH VOL VIH VIL IX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Load Current Output Leakage Current Output Short Circuit Current[5] VCC Operating Supply Current Automatic CE Power-Down Current--TTL Inputs Automatic CE Power-Down Current -- CMOS Inputs GND VI VCC GND VI VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Com'l Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.3 -1 -5 Min. 2.4 Max. VCCQ 0.4 VCC + 0.3V 0.8 1 5 -300 280 2.2 -0.3 -1 -5 7C1031-10 7C1032-10 Min. 2.4 Max. VCCQ 0.4 VCC + 0.3V 0.8 1 5 -300 280 2.2 -0.3 -1 -5 7C1031-12 7C1032-12 Min. 2.4 Max. VCCQ 0.4 VCC + 0.3V 0.8 1 5 -300 230 Unit V V V V A A mA mA
ISB1
Max. VCC, CS Com'l VIH, VIN VIH or VIN VIL, f = fMAX Max. VCC, CS Com'l VCC - 0.3V, VIN VCC - 0.3V or VIN 0.3V, f = 0[6]
80
80
60
mA
ISB2
30
30
30
mA
Capacitance[7]
Parameter CIN: Addresses CIN: Other Inputs COUT Output Capacitance Description Input Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Com'l Com'l Com'l Max. 4.5 5 8 Unit pF pF pF
Notes: 2. Minimum voltage equals -2.0V for pulse durations of less than 20 ns. 3. TA is the case temperature. 4. See the last page for Group A subgroup testing information. 5. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 6. Inputs are disabled, clock is allowed to run at speed. 7. Tested initially and after any design or process changes that may affect these parameters.
5
CY7C1031 CY7C1032
AC Test Loads and Waveforms
R1 OUTPUT Z0 = 50 RL = 50 5 pF VL =1.5V INCLUDING JIGAND SCOPE R2 GND 3 ns VCCQ OUTPUT ALL INPUT PULSES 3.0V 10% 90% 90% 10% 3 ns
(a)
(b)
[8]
1031-3 1031-4
Switching Characteristics Over the Operating Range[9]
7C1031-8 7C1032-8 Parameter tCYC tCH tCL tAS tAH tCDV tDOH tADS tADSH tWES tWEH tADVS tADVH tDS tDH tCSS tCSH tCSOZ tEOZ tEOV tWEOZ tWEOV Clock Cycle Time Clock HIGH Clock LOW Address Set-Up Before CLK Rise Address Hold After CLK Rise Data Output Valid After CLK Rise Data Output Hold After CLK Rise ADSP, ADSC Set-Up Before CLK Rise ADSP, ADSC Hold After CLK Rise WH, WL Set-Up Before CLK Rise WH, WL Hold After CLK Rise ADV Set-Up Before CLK Rise ADV Hold After CLK Rise Data Input Set-Up Before CLK Rise Data Input Hold After CLK Rise Chip Select Set-Up Chip Select Hold After CLK Rise Chip Select Sampled to Output High Z OE HIGH to Output High Z OE LOW to Output Valid WH or WL Sampled LOW to Output High Z[11, 12] WH or WL Sampled HIGH to Output Valid[12]
[11] [11]
7C1031-10 7C1032-10 Min. 20 8 8 2.5 0.5 Max.
7C1031-12 7C1032-12 Min. 20 8 8 2.5 0.5 Max. Unit ns ns ns ns ns 12 3 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 ns ns ns ns ns ns ns ns ns ns ns ns 7 7 6 7 12 ns ns ns ns ns
Description
Min. 15 [10] 5 5 2.5 0.5
Max.
8.5 3 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2 2 6 6 5 5 8.5 3 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2 2
10
6 6 5 6 10
2 2
Notes: 8. Resistor values for VCCQ = 5V are: R1 = 1179 and R2 = 868. Resistor values for VCCQ = 3.3V are R1 = 317 and R2 = 348. 9. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads. 10. Do not use the burst mode, if device operates at a frequency above 50 MHz. 11. t CSOZ, tEOZ, and tWEOZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 12. At any given voltage and temperature, tWEOZ min. is less than tWEOV min.
6
CY7C1031 CY7C1032
Switching Waveforms
Single Read[13]
tCH CLK tCSS CS tAS ADDRESS
[14]
tCL
tCYC
tCSH
tAH
tADS
tADSH
or ADSP ADSC tWES WH, WL
[15]
tWEH
tCDV DATA OUT
tDOH
1031-6
Single Write Timing: Write Initiated by ADSP
tCH CLK tCSS CS tAS ADDRESS tADS ADSP tWES WH, WL
[15]
tCL
tCSH
tAH
tADSH
tWEH
tDS DATA IN
tDH
DATA OUT tEOZ OE
1031-5
Notes: 13. OE is LOW throughout this operation. 14. If ADSP is asserted while CS is HIGH, ADSP will be ignored. 15. ADSP has no effect on ADV, WL, and WH if CS is HIGH.
7
CY7C1031 CY7C1032
Switching Waveforms (continued)
Single Write Timing: Write Initiated by ADSC
tCH CLK tCSS CS tAS ADDRESS tADS ADSC tWES WH, WL tDS DATA IN tDH tWEH tADSH tAH tCSH tCL
DATA OUT tEOZ OE
1031-7
Burst Read Sequence with Four Accesses
CLK tCSS CS tAS ADDRESS tADS tADSH tAH tCSH
ADSP
[14]
or ADSC tADVS tADVH
ADV
[15] [15]
WH,WL
tWES
tWEH
OE tCDV DATA OUT OE DATA0 tDOH DATA1 DATA2 DATA3
1031-8
8
CY7C1031 CY7C1032
Switching Waveforms (continued)
Output (Controlled by OE)
DATA OUT tEOZ OE
1031-9
tEOV
Write Burst Timing: Write Initiated by ADSC
CLK tCSS CS tWES WH, WL tWEH tCSH
OE tADS ADSP
[14]
tADSH
tADS ADSC tAS ADDR
tADSH
tAH
tADVS ADV tDS DATA DATA0 tDH
tADVH
DATA1
DATA2
DATA3
1031-10
9
CY7C1031 CY7C1032
Switching Waveforms (continued)
Write Burst Timing: Write Initiated by ADSP
CLK tCSS CS tCSH
WH, WL
[15]
OE
ADSC tADS ADSP
[14]
tADSH
tAS ADDR
tAH
tADVS tADVH ADV
[15]
tDS DATA
tDH DATA1 DATA2 DATA3
DATA0
1031-11
10
CY7C1031 CY7C1032
Switching Waveforms (continued)
Output Timing (Controlled by CS)
CLK tADS ADSC tADS tADSH tCSS tCSS CS tCDV DATA OUT
1031-12
tADSH
tCSH
tCSH
tCSOZ
Output Timing (Controlled by WH/ WL)
CLK tADS ADSC and ADSP tWES WH, WL tWEOZ DATA OUT
1031-13
tADSH
tADS
tADSH
tWEH
tWEOV
Truth Table
CS H H H H H L L L X X X X ADSP X L L L L L H H H H H H Input ADSC ADV L X H H H H H X L L H H H H L H L X X X L L H H WH or WL X H H L L X H L L H L H CLK LH LH LH LH LH LH LH LH LH LH LH LH Address N/A Same address as previous cycle Incremented burst address Same address as previous cycle Incremented burst address External External External Incremented burst address Incremented burst address Same address as previous cycle Same address as previous cycle Operation Chip deselected Read cycle (ADSP ignored) Read cycle, in burst sequence (ADSP ignored) Write cycle (ADSP ignored) Write cycle, in burst sequence (ADSP ignored) Read cycle, begin burst Read cycle, begin burst Write cycle, begin burst Write cycle, in burst sequence Read cycle, in burst sequence Write cycle Read cycle
11
CY7C1031 CY7C1032
Ordering Information
Speed (ns) 8 10 12 Speed (ns) 8 10 12 Ordering Code CY7C1031-8JC CY7C1031-10JC CY7C1031-12JC Package Name J69 J69 J69 Package Name J69 J69 J69 Package Type 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier Operating Range Commercial Commercial Commercial Operating Range Commercial Commercial Commercial
Ordering Code CY7C1032-8JC CY7C1032-10JC CY7C1032-12JC
Package Type 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier
Document #: 38-00219-C
Package Diagrams
52-Lead Plastic Leaded Chip Carrier J69
51-85004-A
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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